CAS=RESERVED_, RAS=RESERVED_
RAS and CAS latencies for EMC_DYCS0.
| RAS | RAS latency (active to read/write delay). 0 (RESERVED_): Reserved. 1 (ONE_CCLK_CYCLE_): One CCLK cycle. 2 (TWO_CCLK_CYCLES_): Two CCLK cycles. 3 (THREE_CCLK_CYCLES_P): Three CCLK cycles (POR reset value). |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |
| CAS | CAS latency. 0 (RESERVED_): Reserved. 1 (ONE_CCLK_CYCLE_): One CCLK cycle. 2 (TWO_CCLK_CYCLES_): Two CCLK cycles. 3 (THREE_CCLK_CYCLES_P): Three CCLK cycles (POR reset value). |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |